`include "defines.v"
module ysyx_210448_EXE_MEM (
  input clk,
  input wire rst,
  input wire exe_fetched,
  input wire exe_csr_skip,
  input wire exe_mem_read,
  input wire [63:0]exe_pc,
  input wire [31:0] exe_inst,
  input wire [6:0]exe_opcode,
  input wire [6 : 0]exe_s_imm,
  input wire [4 : 0]exe_s_imm_s,
  input wire [63:0]exe_op1,
  input wire [63:0]exe_op2,
  input wire [11:0] exe_I_imm,
  input wire [2:0] exe_s1,
  input wire [4:0] exe_rd,
  input wire exe_w_ena,
  //input wire [63:0] exe_csr_data,
  input wire exe_csr_read,
  input wire exe_csr_write,
  input wire [11:0] exe_csr,
  //input wire [63:0] exe_data,
  input wire exe_mem_en,
  input wire exe_open,
  input wire exe_skip,

  output reg [63:0]mem_pc,
  output reg [31:0] mem_inst,
  output reg mem_fetched,
  output reg mem_csr_skip,
  output reg [6:0]mem_opcode,
  output reg [6:0]mem_s_imm,
  output reg [4:0]mem_s_imm_s,
  output reg [63:0]mem_op1,
  output reg [63:0]mem_op2,
  output reg [11:0] mem_I_imm,
  output reg [4:0] mem_rd,
  output reg mem_w_ena,
  //output reg [63:0] mem_csr_data,
  output reg mem_csr_read,
  output reg mem_csr_write,
  output reg mem_mem_read,
  output reg [11:0] mem_csr,
  //output reg [63:0] mem_data,
  output reg [2:0] mem_s1,
  output reg mem_open,
  output reg mem_skip
);
    always @(posedge clk) begin
        if(rst==1'b1)
        begin
        mem_pc<=64'b0;
        mem_inst<=32'b0;
        mem_opcode<=7'b0;
        mem_s_imm<=7'b0;
        mem_s_imm_s<=5'b0;
        mem_op1<=64'b0;
        mem_op2<=64'b0;
        mem_I_imm<=12'b0;
        mem_s1<=3'b0;
        mem_rd<=5'b0;
        mem_w_ena<=1'b0;
       // mem_csr_data<=64'b0;
        mem_csr_read<=1'b0;
        mem_csr_write<=1'b0;
        mem_csr<=12'b0;
        //mem_data<=64'd0;
        mem_open<=1'b0;
        mem_skip<=1'b0;
        mem_csr_skip<=1'b0;
        mem_fetched<=1'b0;
        mem_mem_read<=1'b0;
        end
        else if(exe_mem_en)
        begin
          mem_pc<=exe_pc;
          mem_inst<=exe_inst;
          mem_opcode<=exe_opcode;
          mem_s_imm<=exe_s_imm;
          mem_s_imm_s<=exe_s_imm_s;
          mem_op1<=exe_op1;
          mem_op2<=exe_op2;
          mem_I_imm<=exe_I_imm;
          mem_s1<=exe_s1;
          mem_rd<=exe_rd;
          mem_w_ena<=exe_w_ena;
         // mem_csr_data<=exe_csr_data;
          mem_csr_read<=exe_csr_read;
          mem_csr_write<=exe_csr_write;
          mem_csr<=exe_csr;
          //mem_data<=exe_data;
          mem_open<=exe_open;
          mem_skip<=exe_skip;
          mem_csr_skip<=exe_csr_skip;
          mem_fetched<=exe_fetched;
          mem_mem_read<=exe_mem_read;
        end
    end
endmodule
